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w39v040fa 512k 8 cmos flash memory with fwh interface publication release date: december 19, 2002 - 1 - revision a2 1. general description the w39v040fa is a 4-megabit, 3.3-volt onl y cmos flash memory organized as 512k 8 bits. for flexible erase capability, the 4mbits of data are di vided into 8 uniform sectors of 64 kbytes, which are composed of 16 smaller even pages with 4 kbyt es. the device can be programmed and erased in- system with a standard 3.3v power supply. a 12-volt vpp is not required. the unique cell architecture of the w39v040fa results in fast program/erase oper ations with extremely low current consumption. this device can operate at two modes, progra mmer bus interface mode and fwh bus interface mode. as in the programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. but in the fwh interface mode, this device complies with the intel fwh specification. the device can also be programmed and er ased using standard eprom programmers. 2. features ? single 3.3-volt operations: ? 3.3-volt read ? 3.3-volt erase ? 3.3-volt program ? fast program operation: ? byte-by-byte programming: 35 s (typ.) ? fast erase operation: ? chip erase 100 ms (max.) ? sector erase 25 ms (max.) ? page erase 25 ms (max.) ? fast read access time: tkq 11 ns ? endurance: 10k cycles (typ.) ? twenty-year data retention ? 8 even sectors with 64k bytes each, which is composed of 16 flexible pages with 4k bytes ? any individual sector or page can be erased ? hardware protection: ? optional 16k byte or 64k byte top boot block with lockout protection ? #tbl & #wp support the whole chip hardware protection ? flexible 4k-page size can be used as parameter blocks ? low power consumption ? active current: 12.5 ma (typ. for fwh mode) ? automatic program and erase timing with internal v pp generation ? end of program or erase detection ? toggle bit ? data polling ? latched address and data ? ttl compatible i/o ? available packages: 32l plcc, 32l stsop, 40l tsop (10 x 20 mm)
w39v040fa - 2 - 3. pin configurations 5 6 7 9 10 11 12 13 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 ^ f w h 1 v v s s d q 6 ^ r s v v # r e s e t v d d r / # c ^ c l k v a 9 ^ f g p i 3 v 32l plcc a 1 0 ^ f g p i 4 v n c dq0(fwh0) a7(fgpi1) a6(fgpi0) a4(#tbl) a3(id3) a2(id2) a1(id1) a0(id0) a5(#wp) ic dq7(rsv) #we(fwh4) #oe(#init) nc a 8 ^ f g p i 2 v d q 2 ^ f w h 2 v d q 3 ^ f w h 3 v d q 4 ^ r s v v d q 5 ^ r s v v v ss nc v dd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 32l stsop 24 23 22 21 #we(fwh4 ) dq4(rsv) dq3(fwh3) dq7(rsv) dq6(rsv) #oe(#init) dq5(rsv) 20 19 18 17 a3(id3) ic r/#c(clk) nc v dd a10(fgpi4) nc a9(fgpi3) a8(fgpi2) #reset a7(fgpi1) a6(fgpi0) a2(id2) a1(id1) a0(id0) dq2(fwh2) dq1(fwh1) dq0(fwh0) a5(#wp) a4(#tbl) v ss v ss v dd nc nc 1 10 40l tsop 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 nc vdd clk a9(fgpi3) a8(fgpi2) nc vss vss vdd dq7(rsv) dq6(rsv) vdd vss nc ic a4(#tbl) a5(#wp) 2 3 4 5 6 7 8 9 11 12 13 14 15 16 18 19 17 20 24 21 22 23 nc nc nc a10(fgpi4) nc #reset nc nc a7(fgpi1) a6(fgpi0) dq5(rsv) dq4(rsv) #we(fwh4) a0(id0) a1(id1) a2(id2) a3(id3) dq3 ( fwh3 ) dq2(fwh2) dq1(fwh1) dq0(fwh0) nc #oe(#init) 4. block diagram program- mer interface 7ffff 00000 20000 1ffff 10000 0ffff #reset ic a[10:0] dq[7:0] #oe #we r/#c fwh interface clk fwh4 fwh[3:0] 70000 6ffff boot block 64k bytes main memory block6 64k bytes main memory block5 64k bytes main memory block4 64k bytes main memory block3 64k bytes main memory block2 64k bytes main memory block0 64k bytes 30000 2ffff 40000 3ffff 50000 4ffff main memory block1 64k bytes 60000 5ffff #init 4k page 4k page 4k page 4k page 4k page 4k page 4k page 4k page 4k page 4k page 4k page 4k page optional 16kbytes as boot block 7ffff 7c000 7bfff 70000 #wp #tbl 5. pin description interface sym. pgm fwh pin name ic * * interface mode selection #reset * * reset #init * initialize #tbl * top boot block lock #wp * write protect clk * clk input fgpi[4:0] * general purpose inputs id[3:0] * identification inputs they are internal pull down to vss fwh[3:0] * address/data inputs fwh4 * fwh cycle initial r/#c * row/column select a[10:0] * address inputs dq[7:0] * data inputs/outputs #oe * output enable #we * write enable v dd * * power supply v ss * * ground rsv * * reserved pins nc * * no connection
w39v040fa publication release date: december 19, 2002 - 3 - revision a2 6. functional description interface mode selection and description this device can operate in two interface modes, one is programmer interface mode, and the other is fwh interface mode. the ic pin of the device provides the control between these two interface modes. these interface modes need to be confi gured before power up or return from #reset . when ic pin is set to high state, the device will be in t he programmer mode; while the ic pin is set to low state (or leaved no connection), it will be in the fw h mode. in programmer mode, this device just behaves like traditional flash parts with 8 data lines. but the row and column address inputs are multiplexed. the row address are mapped to the hi gher internal address a[18:11]. and the column address are mapped to the lower internal address a[ 10:0]. for fwh mode, it complies with the fwh interface specification. through the fwh[3:0] and fwh4 to communicate with the system chipset . read (write) mode in programmer interface mode, the read (write) operation of the w39v040fa is controlled by #oe (#we). the #oe (#we) is held low for the host to obtain (write) data from (t o) the outputs (inputs). #oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when #oe is high. as for in the fw h interface mode, the read or write is determined by the "bit 0 & bit 1 of start cycle ". refer to the fwh cycle definition and timing waveforms for further details. reset operation the #reset input pin can be used in some applicat ion. when #reset pin is at high state, the device is in normal operation mode. when #reset pin is at low state, it will halt the device and all outputs will be at high impedance state. as the high state re-asserted to the #reset pin, the device will return to read or standby mode, it depends on the control signals. boot block operation and hardware protection at initial- #tbl & #wp there are two alternatives to set the boot block. eit her 16k-byte or 64k-byte in the top location of this device can be locked as boot block, which can be used to store boot codes. it is located in the last 16k/64k bytes of the memory with the addr ess range from 7c000(hex)/70000(hex) to 7ffff(hex). see command codes for boot block lockout enable for t he specific code. once this feature is set the data for the designated block cannot be erased or pr ogrammed (programming lockout), other memory locations can be changed by the regular programming method. besides the software method, there is a hardwar e method to protect the top boot block and other sectors. before power on programmer, tie the #tbl pin to low state and then the top boot block will not be programmed/erased. if #wp pin is tied to low state before power on, t he other sectors will not be programmed/erased. in order to detect whether the boot block featur e is set on or not, users can perform software command sequence: enter the product ident ification mode (see command codes for identification/boot block lock out detection for specific code), and then read from address 7fff2(hex). if the dq0/dq1 output data is "1 ," the 64kbytes/16kbyte s boot block programming lockout feature will be activated; if the dq0/dq1 output data is "0," the lockout feature will be inactivated and the boot block can be erased/progra mmed. but the hardware protection will override the software lock setting, i.e., while the #tbl pin is trapped at low state, t he top boot block cannot be
w39v040fa - 4 - programmed/erased whether the output data, dq0/dq1 at the address 7fff2, is "0" or "1". the #tbl will lock the whole 64kbytes top boot block, it will not partially lock the 16kbytes boot block. you can check the dq2/dq3 at the address 7fff2 to see whether the #tbl/#wp pin is in low or high state. if the dq2 is "0", it means the #tbl pin is tied to high state. in such condition, whether boot block can be programmed/erased or not will depend on software setting. on the other hand, if the dq2 is "1", it means the #tbl pin is tied to low state, then boot block is locked no matter how the software is set. like the dq2, the dq3 inversely mirrors the #w p state. if the dq3 is "0", it means the #wp pin is in high state, then all the sectors ex cept the boot block can be programm ed/erased. on the other hand, if the dq3 is "1", then all the sectors except the boot block are progra mmed/erased inhibited. to return to normal operation, perform a three- byte command sequence (or an alternate single-byte command) to exit the identification mode. fo r the specific code, see command codes for identification/boot blo ck lockout detection. chip erase operation the chip-erase mode can be initiated by a si x-byte command sequence. after the command loading cycle, the device enters the inte rnal chip erase mode, which is automatically timed and will be completed within fast 100 ms (max). the host system is not required to provide any control or timing during this operation. if the boot block programming lo ckout is activated, only the data in the other memory sectors will be erased to ff(hex) while the data in the boot block will not be erased (remains as the same state before the chip erase operation) . the entire memory array will be erased to ff(hex) by the chip erase operation if t he boot block programming lockout feat ure is not activated. the device will automatically return to normal read mode after the erase operation completed. data polling and/or toggle bits can be used to detect end of erase cycle. sector/page erase command sector/page erase is a six bus cycles operation. t here are two "unlock" write cycles, followed by writing the "set-up" command. two more "unlock" write cycles then follows by the sector/page erase command. the sector/page address (any address loca tion within the desired sector/page) is latched on the falling edge of #we, while the command (30h /50h) is latched on the rising edge of #we. sector/page erase does not require the user to pr ogram the device prior to erase. when erasing a sector/page or sectors/pages the remaining unselect ed sectors/pages are not a ffected. the system is not required to provide any controls or timings during these operations. the automatic sector/page erase begins after the er ase command is completed, right from the rising edge of the #we pulse for the last sector/page erase command pulse and terminates when the data on dq7, data polling, is "1" at which time the dev ice returns to the read mode. data polling must be performed at an address within any of the sectors/pages being erased. refer to the erase command flow chart usi ng typical command strings and bus operations. program operation the w39v040fa is programmed on a byte-by-byte basis. program operation can only change logical data "1" to logical data "0." the erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. the program operation is initiated by a 4-by te command cycle (see command codes for byte programming). the device will internally enter t he program operation immediately after the byte- program command is entered. the internal progr am timer will automatically time-out (50 s max. - t bp ) once it is completed and then return to normal read mode. data polling and/or toggle bits can be used to detect end of program cycle.
w39v040fa publication release date: december 19, 2002 - 5 - revision a2 hardware data protection the integrity of the data stored in the w39v040fa is also hardware protected in the following ways: (1) noise/glitch protection: a #we pulse of less than 15 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the programming and read operation are inhibited when v dd is less than 1.5v typical. (3) write inhibit mode: forcing #oe low or #we hi gh will inhibit the write operation. this prevents inadvertent writes during pow er-up or power-down periods. (4) v dd power-on delay: when v dd has reached its sense level, the device will automatically time-out 5 ms before any write (erase/program) operation. data polling (dq 7 )- write status detection the w39v040fa includes a data polling feature to indi cate the end of a program or erase cycle. when the w39v040fa is in the internal program or erase cycle, any attempts to read dq 7 of the last byte loaded will receive the complement of the tr ue data. once the program or erase cycle is completed, dq 7 will show the true data. note that dq 7 will show logical "0" during the erase cycle, and when erase cycle has been completed it becomes logical "1" or true data. toggle bit (dq 6 )- write status detection in addition to data polling, the w39v040fa provi des another method for determining the end of a program cycle. during the internal program or er ase cycle, any consecutive attempts to read dq 6 will produce alternating 0's and 1's. when the program or erase cycle is completed, this toggling between 0's and 1's will stop. the device is then ready for the next operation. register there are three kinds of registers on this device, the general purpose input registers, the block lock control registers and product ident ification registers. users c an access these registers through respective address in the 4gbytes memory map. t here are detail descriptions in the sections below. general purpose inputs register this register reads the fgpi[4:0] pins on the w 39v040fa.this is a pass-through register which can read via memory address ffbc0100(hex). since it is pass-through register, there is no default value. gpi register table bit function 7 ? 5 reserved 4 read fgpi4 pin status 3 read fgpi3 pin status 2 read fgpi2 pin status 1 read fgpi1 pin status 0 read fgpi0 pin status
w39v040fa - 6 - block locking registers this part provides 8 even 64kbytes blocks, and each block can be locked by register control. these control registers can be set or clear through me mory address. below is the detail description. block locking registers type and access memory map table registers registers type control block device physical address 4gbytes system memory address blr7 r/w 7 7ffffh ? 70000h ffbf0002h blr6 r/w 6 6ffffh ? 60000h ffbe0002h blr5 r/w 5 5ffffh ? 50000h ffbd0002h blr4 r/w 4 4ffffh ? 40000h ffbc0002h blr3 r/w 3 3ffffh ? 30000h ffbb0002h blr2 r/w 2 2ffffh ? 20000h ffba0002h blr1 r/w 1 1ffffh ? 10000h ffb90002h blr0 r/w 0 0ffffh ? 00000h ffb80002h block locking register bits function table bit function 7 ? 3 reserved 2 read lock 1: prohibit to read in the block where set 0: normal read operation in the block where clear. this is default state. 1 lock down 1: prohibit further to set or clear the read lock or write lock bits. this lock down bit can only be set not clear. only the dev ice is reset or re-powered, the lock down bit is cleared. 0: normal operation for read lock or wri te lock. this is the default state. 0 write lock 1: prohibited to write in the blo ck where set. this is default state. 0: normal programming/erase operation in the block where clear. register based block locking value definitions table bit [7:3] bit 2 bit 1 bit 0 result 00000 0 0 0 full access. 00000 0 0 1 write lock. default state. 00000 0 1 0 locked open (full access, lock down). 00000 0 1 1 write locked, locked down. 00000 1 0 0 read locked. 00000 1 0 1 read & write locked. 00000 1 1 0 read locked, locked down. 00000 1 1 1 read & write locked, locked down.
w39v040fa publication release date: december 19, 2002 - 7 - revision a2 read lock any attempt to read the data of read locked block will result in ?00.? the defaul t state of any block is unlocked upon power up. user can clear or set the wr ite lock bit anytime as long as the lock down bit is not set. write lock this is the default state of blocks upon power up. befo re any program or erase to the specified block, user should clear the write lock bit first. user can cl ear or set the write lock bit anytime as long as the lock down bit is not set. the write lock function is in conjunction with the hardw are protect pins, #wp & tbl. when hardware protect pins are enabled, it w ill override the register block locking functions and write lock the blocks no matter how the status of t he register bits. reading the register bit will not reflect the status of the #wp or #tbl pins. lock down the default state of lock down bit for any block is unl ocked. this bit can be set only once; any further attempt to set or clear is ignored. only the rese t from #reset or #init can clear the lock down bit. once the lock down bit is set for a block, then the wr ite lock bit & read lock bit of that block will not be set or cleared, and keep its current state. product identification registers in the fwh interface mode, a read from ffb c, 0000(hex) can output t he manufacturer code, da(hex). a read from ffbc, 0001(hex) can output the device code 34(hex). there is an alternative software method (six commands bytes) to read out the product identification in both the programmer interface mode and the fwh in terface mode. thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms. in the software access mode, a six-byte (o r jedec 3-byte) command sequence can be used to access the product id for programmer interfac e mode. a read from address 0000(hex) outputs the manufacturer code, da(hex). a read from addre ss 0001(hex) outputs the devic e code, 34(hex).? the product id operation can be terminated by a thr ee-byte command sequence or an alternate one-byte command sequence (see command definition table for detail). table of operating mode operating mode selection - programmer mode pins mode #oe #we #reset address dq. read v il v ih v ih ain dout write v ih v il v ih ain din standby x x v il x high z v il x v ih x high z/dout write inhibit x v ih v ih x high z/dout output disable v ih x v ih x high z
w39v040fa - 8 - operating mode selection - fwh mode operation modes in fwh interface mode are determi ned by "start cycle" w hen it is selected. when it is not selected, its output s (fwh[3:0]) will be disable. please reference to the "fwh cycle definition". table of command definition command no. of 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle description cycles (1) addr. data addr. data addr. da ta addr. data addr. data addr. data read 1 a in d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (5) 30 page erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 pa (6) 50 byte program 4 5555 aa 2aaa 55 5555 a0 a in d in top boot block lockout ? 64k/16kbyte 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40/70 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (4) 3 5555 aa 2aaa 55 5555 f0 product id exit (4) 1 xxxx f0 notes: 1. the cycle means the write command cycle not the fwh clock cycle. 2. the column address / row address are mapped to the low / high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[18:11] 3. address format: a14 ? a0 (hex); data format: dq7-dq0 (hex) 4. either one of the two product id exit commands can be used. 5. sa: sector address sa = 7xxxxh for unique sector7 (boot sector) sa = 3xxxxh for unique sector3 sa = 6xxxxh for unique sector6 sa = 2xxxxh for unique sector2 sa = 5xxxxh for unique sector5 sa = 1xxxxh for unique sector1 sa = 4xxxxh for unique sector4 sa = 0xxxxh for unique sector0 6. pa : page address pa = 7fxxxh for page 15 in sector 7 pa = 7exxxh for page 14 in sector 7 pa = 7dxxxh for page 13 in sector 7 pa = 7cxxxh for page 12 in sector 7 pa = 7bxxxh for page 11 in sector 7 pa = 7axxxh for page 10 in sector 7 pa = 79xxxh for page 9 in sector 7 pa = 78xxxh for page 8 in sector 7 pa = 77xxxh for page 7 in sector 7 pa = 76xxxh for page 6 in sector 7 pa = 75xxxh for page 5 in sector 7 pa = 74xxxh for page 4 in sector 7 pa = 73xxxh for page 3 in sector 7 pa = 72xxxh for page 2 in sector 7 pa = 71xxxh for page 1 in sector 7 pa = 70xxxh for page 0 in sector 7 pa = 6fxxxh to 60xxxh for page 15 to page 0 in sector 6 (reference to the first column) pa = 5fxxxh to 50xxxh for page 15 to page 0 in sector 5 (reference to the first column) pa = 4fxxxh to 40xxxh for page 15 to page 0 in sector 4 (reference to the first column) pa = 3fxxxh to 30xxxh for page 15 to page 0 in sector 3 (reference to the first column) pa = 2fxxxh to 20xxxh for page 15 to page 0 in sector 2 (reference to the first column) pa = 1fxxxh to 10xxxh for page 15 to page 0 in sector 1 (reference to the first column) pa = 0fxxxh to 00xxxh for page 15 to page 0 in sector 0 (reference to the first column)
w39v040fa publication release date: december 19, 2002 - 9 - revision a2 fwh cycle definition field no. of clocks description start 1 "1101b" indicates fwh memory read cy cle; while "1110b" indicates fwh memory write cycle. 0000b" appears on fwh bus to indicate the initial idsel 1 this one clock field indicates which fwh component is being selected. msize 1 memory size. there is always show ?0000b? for single byte access. tar 2 turned around time addr 7 address phase for memory cycle. fwh supports the 28 bits address protocol. the addresses transfer most significant nibble first and least significant nibble last. (i.e. a ddress[27:24] on fwh[3:0] first, and address[3:0] on fwh[3:0] last.) sync n synchronous to add wait state. "0000b" means ready, "0101b" means short wait, "0110b" means long wait, "1001b" for dma only, "1010b" means error, and other values are reserved. data 2 data phase for memory cycle. the data transfer least significant nibble first and most significant nibble last. (i.e. dq[3:0] on fwh[3:0] first, then dq[7:4] on fwh[3:0] last.)
w39v040fa - 10 - embedded programming algorithm start write program command sequence (see below) increment address programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data #data polling/ toggle bit last address ? no yes program command sequence (address/command): pause t bp
w39v040fa publication release date: december 19, 2002 - 11 - revision a2 embedded erase algorithm start write erase command sequence (see below) erasure completed #data polling or toggle bit successfully completed 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h 5555h/10h chip erase command sequence (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h sector address/30h (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h page address/50h individual page erase (address/command): individual sector erase command sequence command sequence pause t ec /t sec /t pec
w39v040fa - 12 - embedded #data polling algorithm start read byte (dq0 - dq7) address = va pass dq7 = data ? yes no va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = any of the device addresses being erased during chip erase operation = any of the page addresses within the page being erased during page erase operation embedded toggle bit algorithm start read byte (dq0 - dq7) address = don't care dq6 = toggle ? yes no pass
w39v040fa publication release date: december 19, 2002 - 13 - revision a2 software product identification and boot block lockout detection acquisition flow product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout detection mode (3) read address = 00000 data = da read address = 00001 data = 34 read address = 7fff2 check dq[3:0] of data outputs (4) product identification exit(6) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5) (2) (2) load data aa to address 5555 load data aa to address 5555 pause 10 s notes for software product identificat ion/boot block lockout detection: (1) data format: dq7 ? dq0 (hex); address format: a14 ? a0 (hex) (2) a1 ? a18 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification and boot block lockout detection mode if power down. (4) the dq[3:0] to indicate the sectors protect status as below: dq0 dq1 dq2 dq3 0 64k boot block unlocked by software 16kbytes boot block unlocked by software 64kbytes boot block unlocked by #tbl hardware trapping whole chip unlocked by #wp hardware trapping except boot block 1 64k boot block locked by software 16kbytes boot block locked by software 64kbytes boot block locked by #tbl hardware trapping whole chip locked by #wp hardware trapping except boot block (5) the device returns to standard operation mode. (6) optional 1-write cycle (write f0 (hex.) at xxxx address) c an be used to exit the product identification/boot block lockout detection.
w39v040fa - 14 - boot block lockout enable acquisition flow boot block lockout feature set flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40/70 to address 5555 exit 40 to lock 64k boot block 70 to lcok 16k boot block pause t bp
w39v040fa publication release date: december 19, 2002 - 15 - revision a2 7. dc characteristics absolute maximum ratings parameter rating unit power supply voltage to v ss potential -0.5 to +4.6 v operating temperature 0 to +70 c storage temperature -65 to +150 c d.c. voltage on any pin to ground potential -0.5 to v dd +0.5 v transient voltage (<20 ns) on any pin to ground potential -1.0 to v dd +0.5 v note: exposure to conditions beyond those lis ted under absolute maximum ratings may adversely affect the life and reliability of the device. programmer interface mode dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply current i cc in read or write mode, all dqs open address inputs = 3.0v/0v, at f = 3 mhz - 10 20 ma input leakage current i li v in = v ss to v dd - - 90 a output leakage current i lo v out = v ss to v dd - - 90 a input low voltage v il - -0.5 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = -0.1ma 2.4 - - v
w39v040fa - 16 - fwh interface mode dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply current i cc all i out = 0a, clk = 33 mhz, in fwh mode operation. - 12.5 20 ma standby current 1 isb1 fwh4 = 0.9 v dd , clk = 33 mhz, all inputs = 0.9 v dd / 0.1 v dd no internal operation - 5 25 ua standby current 2 isb2 fwh4 = 0.1 v dd , clk = 33 mhz, all inputs = 0.9 v dd /0.1 v dd no internal operation. - 3 10 ma input low voltage v il - -0.5 - 0.3 v dd v input low voltage of #init v ili - -0.5 - 0.2 v dd v input high voltage v ih - 0.5 v dd - v dd +0.5 v input high voltage of #init pin v ihi - 1.35 v - v dd +0.5 v output low voltage v ol i ol = 1.5 ma - - 0.1 v dd v output high voltage v oh i oh = -0.5 ma 0.9 v dd - - v power-up timing parameter symbol typical unit power-up to read operation t pu . read 100 s power-up to write operation t pu . write 5 ms capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf
w39v040fa publication release date: december 19, 2002 - 17 - revision a2 8. programmer interface mode ac characteristics ac test conditions parameter conditions input pulse levels 0v to 0.9 v dd input rise/fall time < 5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate and c l = 30 pf ac test load and waveform +3.3v 1.8k 1.3k d out ? ? 30 pf (including jig and scope) input 0.9vdd 0v test point test point 1.5v 1.5v output
w39v040fa - 18 - programmer interface mode ac characteristics, continued read cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) w39v040fa parameter symbol min. max. unit read cycle time t rc 300 - ns row / column address set up time t as 50 - ns row / column address hold time t ah 50 - ns address access time t aa - 150 ns output enable access time t oe - 75 ns #oe low to active output t olz 0 - ns #oe high to high-z output t ohz - 35 ns output hold from address change t oh 0 - ns write cycle timing parameters parameter symbol min. typ. max. unit reset time t rst 1 - - s address setup time t as 50 - - ns address hold time t ah 50 - - ns r/#c to write enable high time t cwh 50 - - ns #we pulse width t wp 100 - - ns #we high width t wph 100 - - ns data setup time t ds 50 - - ns data hold time t dh 50 - - ns #oe hold time t oeh 0 - - ns byte programming time t bp - 35 50 s sector/page erase cycle time t pec - 20 25 ms chip erase cycle time t ec - 75 100 ms note: all ac timing signals observe the following guide lines for determining setup and hold times: (a) high level signal's reference le vel is input high and (b) low level si gnal's reference level is input low. ref. to the ac testing condition. data polling and toggle bit timing parameters w39v040fa unit parameter symbol min. max. #oe to data polling output delay t oep - 40 ns #oe to toggle bit output delay t oet - 40 ns
w39v040fa publication release date: december 19, 2002 - 19 - revision a2 9. timing waveforms for programmer interface mode read cycle timing diagram dq[7:0] high-z #oe #we v ih t oh t aa data valid t ohz high-z t olz t oe #reset a[10:0] t rc #c r/ t as t ah row address column address t as t ah column address row address t rst write cycle timing diagram data valid t cwh t oeh t wp t ds t as t ah t wph t dh dq[7:0] #oe #we #c r/ #reset a[10:0] column address row address t rst t as t ah
w39v040fa - 20 - timing waveforms for programmer interface mode, continued program cycle timing diagram a[10:0] byte 0 byte 1 byte 2 internal write start dq[7:0] #oe #we byte program cycle t bp t wph t wp 5555 5555 2aaa aa a0 55 programmed address data-in byte 3 note: the internal address a[18:0] are converted from external column/row addres s column/row address are mapped to the low/high order internal address . i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[18:11]. #c r/ (internal a[18:0]) #data polling timing diagram a[10:0] dq7 #we #oe x x x t oep t ec t bp or #c r/ x (internal a[18:0]) an an an an
w39v040fa publication release date: december 19, 2002 - 21 - revision a2 timing waveforms for programmer interface mode, continued toggle bit timing diagram a[10:0] dq6 #we #oe t oet t ec t bp or #c r/ boot block lockout enable timing diagram sb2 sb1 sb0 dq[7:0] #oe #we sb3 sb4 sb5 t wp t wph aa 55 80 40/70 aa 55 note: the internal address a[18:0] are converted from external column/row ad d column/row address are mapped to the low/high order internal add r i.e. column address a[10:0] are mapped to the internal a[10: row address a[7:0] are mapped to the internal a[18:1 1 (internal a[18:0]) six-byte code for boot block lockout command 5555 2aaa 5555 5555 2aaa 5555 a[10:0] #c r/ t wc when 40(hex) is loaded, the 64kbyte are locked; while 70(hex) is loaded, the 16kbyte is l o
w39v040fa - 22 - timing waveforms for programmer interface mode, continued chip erase timing diagram dq[7:0] aa 55 80 aa 55 10 sb2 sb1 sb0 #oe #we sb3 sb4 sb5 internal erasure starts t wp t wph t ec #c r/ note: the internal address a[18:0] are converted from external column/row addr e column/row address are mapped to the low/high order internal addre i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[18:11]. (internal a[18:0]) six-byte code for 3.3v-only software chip erase 5555 2aaa 5555 5555 2aaa 5555 a[10:0] sector/page erase timing diagram sb2 sb1 sb0 a[10:0] dq[7:0] #oe #we sb3 sb4 sb5 internal erase starts six-byte code for 3.3v-only sector/page erase t wp t wph t pec 5555 2aaa 5555 5555 2aaa sa/pa aa 55 80 aa 55 30/50 sa = sector address and pa = page address, please ref. to the "table of command definition " note: the internal address a[18:0] are converted from external column/row addres s column/row address are mapped to the low/high order internal address i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[18:11]. #c r/ (internal a[18:0])
w39v040fa publication release date: december 19, 2002 - 23 - revision a2 10. fwh interface mode ac characteristics ac test conditions parameter conditions input pulse levels 0.6 v dd to 0.2 v dd input rise/fall slew rate 1 v/ns input/output timing level 0.4v dd / 0.4v dd output load 1 ttl gate and c l = 10 pf read/write cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) w39v040fa parameter symbol min. max. unit clock cycle time t cyc 30 - ns input set up time t su 7 - ns input hold time t hd 0 - ns clock to data valid t kq 2 11 ns note: minimum and maximum time has different loads . please refer to pci specification. reset timing parameters parameter symbol min. typ. max. unit v dd stable to reset active t prst 1 - - ms clock stable to reset active t krst 100 - - s reset pulse width t rstp 100 - - ns reset active to output float t rstf - - 50 ns reset inactive to input active t rst 10 - - s note: all ac timing signals observe the following guide lines for determining setup and hold times: (a) high level signal's reference le vel is input high and (b) low level si gnal's reference level is input low. ref. to the ac testing condition.
w39v040fa - 24 - 11. timing waveforms for fwh interface mode read cycle timing diagram t cyc fwh4 #reset fwh[3:0] start fwh read idsel clk 1 clock 2 clocks a[15:12] address sync tar 1111b tri-state 0000b t kq t hd t su a[11:8] a[7:4] 0000 b] data out 2 clocks d[7:4] data d[3:0] next start 1 clock 0000b t hd t su load address in 7 clocks a[3:0] m size xxxxb xa[22]xxb xxa[18:16] 1 clock 1 clock 0000b 1101b note: when a22 = high, the host will read the bios code from the fwh d while a22 = low, the host will read the gpi (add = ffbc010 0 product id (add = ffbc0000/ffbc0001) from the fwh de v 1111b tri-state 2 clocks tar write cycle timing diagram t cyc fwh4 #reset fwh[3:0] start fwh write idsel clk next star t 1 clock 1 clock a[15:12] load data in 2 clocks d[7:4] address sync 2 clocks tar data 1111b tri-state 0000b t hd t su a[11:8] a[7:4] 0000b d[3:0] 0000b load address in 7 clocks a[3:0] m size xxxxb xxxxb xxa[18:16]b 1 clock 1 clock 0000b 1110b 2 clocks tar 1111b tri-state
w39v040fa publication release date: december 19, 2002 - 25 - revision a2 timing waveforms, for fwh interface mode, continued program cycle timing diagram fwh4 #reset fwh[3:0 ] 1st start idsel load address "5555" in 7 clocks clk 1 clock 2 clocks load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in fwh mode. 2nd start load address "2aaa" in 7 clocks 1 clock 2 clocks load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in fwh mode. 3rd start load address "5555" in 7 clocks 1 clock 2 clocks load data "a0" in 2 clocks 1010b 0000b write the 3rd command to the device in fwh mode. 4th start load ain in 7 clocks fwh4 #reset fwh[3:0 ] clk fwh4 #reset fwh[3:0 ] clk fwh4 #reset fwh[3:0 ] clk sync internal program start tar 1 clock 2 clocks a[15:12] load din in 2 clocks d[7:4] write the 4th command(target location to be programmed) to the device in fwh mode. a[11:8] a[7:4] a[3:0] d[3:0] 1111b tri-state 0000b data address address address address sync tar data sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b idsel internal program start idsel idsel 0000b 0000b 0000b 0000b x101b 0101b 0101b 0101b x010b 1010b 1010b 1010b x101b 0101b 0101b 0101b m size m size m size m size xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xa[18:16]b xxxxb xxxxb xxxxb xxxxb 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b start next command 1 clock 2 clocks tar 1111b tri-state start next command 1 clock 2 clocks tar 1111b tri-state start next command 1 clock 2 clocks tar 1111b tri-state tar 2 clocks 1111b tri-state
w39v040fa - 26 - timing waveforms for fwh interface mode, continued #data polling timing diagram read the dq7 to see if the internal write complete or not. fwh4 #reset fwh[3:0] start load address in 7 clocks clk 1 clock 2 clocks xxxxb an[15:12] address sync tar 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] data out 2 clocks dn7,xxx data xxxxb fwh4 #reset fwh[3:0] start load address in 7 clocks clk 1 clock 2 clocks address sync tar 1111b tri-state 0000b data out 2 clocks data when internal write complete, the dq7 will equal to dn7. dn7,xxx xxxxb an[15:12] an[11:8] an[7:4] an[3:0] fwh4 #reset fwh[3:0] start load address "an" in 7 clocks clk 1 clock 2 clocks an[15:12] load data "dn" in 2 clocks dn[7:4] write the last command(program or erase) to the device in fwh mode. address sync tar data 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] dn[3:0] idsel idsel idsel 0000b 0000b 0000b m size m size m size xxxxb xxa[18:16]b xxxxb xxxxb xxa[18:16]b xxxxb xxxxb xxa[18:16]b xxxxb 1 clock 2 clocks tar 1111b tri-state next start 1 clock 2 clocks tar 1111b tri-state next start 1 clock 2 clocks tar 1111b tri-state next start 1 clock 1 clock 0000b 1101b 1 clock 1 clock 0000b 1101b 1 clock 1 clock 0000b 1110b
w39v040fa publication release date: december 19, 2002 - 27 - revision a2 timing waveforms for fwh interface mode, continued toggle bit timing diagram read the dq6 to see if the internal write complete or not. fwh4 #reset start load address in 7 clocks clk 1 clock 2 clocks address sync tar 1111b tri-state 0000b data out 2 clocks x,d6,xxb data xxxxb fwh4 #reset fwh[3:0] start load address in 7 clocks clk 1 clock 2 clocks address sync tar 1111b tri-state 0000b data out 2 clocks data when internal write complete, the dq6 will stop toggle. x,d6,xxb xxxxb fwh4 #reset fwh[3:0] start load address "an" in 7 clocks clk 1 clock 2 clocks a[15:12] load data "dn" in 2 clocks d[7:4] write the last command(program or erase) to the device in fwh mode. address sync tar data 1111b tri-state 0000b a[11:8] a[7:4] a[3:0] d[3:0] idsel xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb idsel idsel 0000b 0000b 0000b m size m size m size xxxxb xxxxb xxxxb xxxxb xxxxb xxa[18:16]b xxxxb xxxxb xxxxb 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1101b 1 clock 1 clock 0000b 1101b 1 clock 2 clocks tar 1111b tri-state next start 1 clock 2 clocks tar 1111b tri-state next start 1 clock 2 clocks tar 1111b tri-state next start fwh[3:0]
w39v040fa - 28 - timing waveforms for fwh interface mode, continued boot block lockout enable timing diagram clk #reset fwh4 fwh[3:0] 1st start load address "5555" in 7 clocks 1 clock 2 clocks x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in fwh mode. address sync tar data 1111b tri-state 0000b idsel 0000b m size xxxxb xxxxb xxxxb start next command 1 clock 2 clocks tar 1111b tri-state 1 clock 1 clock 0000b 1110b clk #reset 2nd start load address "2aaa" in 7 clocks 1 clocks 2 clocks x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in fwh mode. address sync tar data 1111b tri-state 0000b idsel 0000b m size xxxxb xxxxb xxxxb start next command 1 clock 2 clocks tar 1111b tri-state 1 clock 1 clock 0000b 1110b fwh4 fwh[3:0] clk #reset 3rd start load address "5555" in 7 clocks 1 clock 2 clocks x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in fwh mode. address sync tar data 1111b tri-state 0000b idsel 0000b m size xxxxb xxxxb xxxxb start next command 1 clock 2 clocks tar 1111b tri-state 1 clock 1 clock 0000b 1110b fwh4 fwh[3:0] clk #reset 4th start load address "5555" in 7 clocks 1 clock 2 clocks x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in fwh mode. address sync tar data 1111b tri-state 0000b idsel 0000b m size xxxxb xxxxb xxxxb start next command 1 clock 2 clocks tar 1111b tri-state 1 clock 1 clock 0000b 1110b fwh4 fwh[3:0] clk #reset 5th start load address "2aaa" in 7 clocks 1 clock 2 clocks x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in fwh mode. address sync tar data 1111b tri-state 0000b idsel 0000b m size xxxxb xxxxb xxxxb start next command 1 clock 2 clocks tar 1111b tri-state 1 clock 1 clock 0000b 1110b fwh4 fwh[3:0] clk #reset 6th start load address "5555" 7 clocks sync tar 1 clock 2 clocks x101b load data "40" or "70" in two clocks 0100b/ 0111b write the 6th command to the device in fwh mode. 0101b 0101b 0101b 0000b 1111b tri-state 0000b data address idsel 0000b m size xxxxb xxxxb xxxxb 1 clock 1 clock 0000b 1110b fwh4 fwh[3:0] start next command 1 clock 2 clocks tar 1111b tri-state
w39v040fa publication release date: december 19, 2002 - 29 - revision a2 timing waveforms for fwh interface mode, continued chip erase timing diagram load address "5555" in 7 clocks sync internal erase start tar 1 clock x101b load data "10" in 2 clocks 0001b write the 6th command to the device in fwh mode. 0101b 0101b 0101b 0000b 1111b tri-state 0000b data address fwh4 #reset fwh[3:0] 1st start clk x101b 0101b 0101b 0101b 1010b 1010b fwh4 #reset fwh[3:0] clk fwh4 #reset fwh[3:0] clk fwh4 #reset fwh[3:0] clk address sync tar data load address "5555" in 7 clocks 1 clock 2 clocks load data "aa" in 2 clocks write the 1st command to the device in fwh mode. load address "2aaa" in 7 clocks 1 clock 2 clocks x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in fwh mode. load address "5555" in 7 clocks 1 clock 2 clocks x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in fwh mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b load address "5555" in 7 clocks 1 clock 2 clocks x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in fwh mode. load address "2aaa" in 7 clocks 1 clock 2 clocks x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in fwh mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b fwh4 #reset fwh[3:0] clk fwh4 #reset fwh[3:0] clk 2 clocks idsel 0000b 0000b 0000b 0000b 0000b 0000b m size m size m size m size m size m size xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb start next command 1 clock 2 clocks tar 1111b tri-state start next command 1 clock 2 clocks tar 1111b tri-state start next command 1 clock 2 clocks tar 1111b tri-state start next command 1 clock 2 clocks tar 1111b tri-state start next command 1 clock 2 clocks tar 1111b tri-state internal erase start tar 2 clocks 1111b tri-state 6th start idsel 5th start idsel 4th start idsel 3th start idsel 2th start idsel 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b 1 clock 1 clock 0000b 1110b
w39v040fa - 30 - timing waveforms for fwh interface mode, continued sector erase timing diagram 6th start load sector address in 7 clocks sync internal erase start 1 clock load din in 2 clocks 0011b write the 6th command(target sector to be erased) to the device in fwh mode. 0000b tar 2 clocks 1111b tri-state 0000b data address #reset 1st start load address "5555" in 7 clocks clk 1 clock 1 clock start next command 1 clock 2 clocks 1 clock x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in fwh mode. fwh4 #reset fwh[3:0] clk fwh4 #reset fwh[3:0] clk fwh4 #reset clk address sync tar data 2nd start load address "2aaa" in 7 clocks 1 clock 1 clock start next command 1 clock 2 clocks 1 clock x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in fwh mode. 3rd start load address "5555" in 7 clocks 1 clocks 1 clocks start next command 1 clocks 2 clocks 1 clocks x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in fwh mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b 4th start load address "5555" in 7 clocks 1 clock 1 clock start next command 1 clock 2 clocks 1 clock x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in fwh mode. 5th start load address "2aaa" in 7 clocks 1 clock 1 clock start next command 1 clock 1 clock x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in fwh mode. address address sync 2 clocks tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b fwh4 #reset fwh[3:0] clk fwh4 #reset fwh[3:0] clk xxxxb xxxxb xxxxb idsel internal erase start 0000b 1110b idsel 0000b 1110b idsel 0000b 1110b idsel 0000b 1110b idsel 0000b 1110b idsel 0000b 0000b 0000b 0000b 0000b 0000b m size m size m size m size m size m size xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xa[18:16]b xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb tar 2 clocks 1111b tri-state 2 clocks tar 1111b tri-state 2 clocks tar 1111b tri-state 2 clocks tar 1111b tri-state 2 clocks tar 1111b tri-state 2 clocks tar 1111b tri-state 1 clock 1 clock 0000b 1110b fwh[3:0] fwh4 fwh[3:0] xxxxb
w39v040fa publication release date: december 19, 2002 - 31 - revision a2 timing waveforms for fwh interface mode, continued page erase timing diagram clk #reset fwh4 1st start load address "5555" in 7 clocks 1 clock 1 clock start next command 1 clock 2 clocks 1 clock x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in fwh mode. address sync tar data 1111b tri-state 0000b 0000b 1110b idsel 0000b m size xxxxb xxxxb xxxxb 2 clocks tar 1111b tri-state #reset clk fwh4 fwh[3:0] #reset clk 2nd start load address "2aaa" in 7 clocks 1 clock 1 clock start next command 1 clock 2 clocks 1 clock x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in fwh mode. address sync tar data 1111b tri-state 0000b 0000b 1110b idsel 0000b m size xxxxb xxxxb xxxxb 2 clocks tar 1111b tri-state fwh4 fwh[3:0] #reset clk 3rd start load address "5555" in 7 clocks 1 clocks 1 clocks start next command 1 clocks 2 clocks 1 clocks x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in fwh mode. address sync tar data 1111b tri-state 0000b 0000b 1110b idsel 0000b m size xxxxb xxxxb xxxxb 2 clocks tar 1111b tri-state fwh4 4th start load address "5555" in 7 clocks 1 clock 1 clock start next command 1 clock 2 clocks 1 clock x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in fwh mode. address sync tar data 1111b tri-state 0000b #reset clk 0000b 1110b idsel 0000b m size xxxxb xxxxb xxxxb 2 clocks tar 1111b tri-state 5th start load address "2aaa" in 7 clocks 1 clock 1 clock start next command 1 clock 1 clock x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in fwh mode. address sync 2 clocks tar data 1111b tri-state 0000b fwh4 fwh[3:0] 0000b 1110b idsel 0000b m size xxxxb xxxxb xxxxb 2 clocks tar 1111b tri-state #reset clk 6th start load page address in 7 clocks sync internal erase start 1 clock a[15:12] load din in 2 clocks 0101b write the 6th command(target page to be erased) to the device in fwh mode. 0000b tar 2 clocks 1111b tri-state 0000b data address fwh4 fwh[3:0] xxxxb xxxxb xxxxb idsel internal erase start 0000b m size xxxxb xa[18:16]b xxxxb tar 2 clocks 1111b tri-state 1 clock 1 clock 0000b 1110b fwh[3:0] fwh[3:0]
w39v040fa - 32 - timing waveforms for fwh interface mode, continued fgpi register/product id readout timing diagram note: during the gpi read out mode, the dq[4:0] will capture the states(high or low) of the fgpi[4:0] input pins. the dq[7:5] a re reserved pin s #reset fwh[3:0] start idsel load address "ffbc0100(hex)" in 7 clocks for gpi register & "ffbc0000(hex)/ffbc0001(hex) for product id clk 1 clock 1 clock next st a 1 clock 2 clocks 1 cloc k 0000b 1101b address sync tar 1111b tri-state 0000b data out 2 clocks d[7:4] data 0000b 0001b /0000b 0000b 0000b /0001b d[3:0] a[27:24] a[23:20] a[19:16] 0000b m size 2 clocks tar 1111b tri-state fwh4 reset timing diagram clk vdd #reset fwh[3:0] t prst t krst t rstp t rst f t rst fwh4
w39v040fa publication release date: december 19, 2002 - 33 - revision a2 12. ordering information part no. access time (ns) power supply current max. (ma) standby vdd current max. (ma) package w39v040fap 11 20 10 32l plcc w39v040faq 11 20 10 32l stsop W39V040FAT 11 20 10 40l tsop notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 13. how to read the top marking example: the top marking of 32-pin stsop w39v040faq 1 st line: winbond logo 2 nd line: the part number: w39v040faq 3 rd line: the lot number 4 th line: the tracking code: 149 o b sa 149: packages made in '01, week 49 o: assembly house id: a means ase, o means ose, ...etc. b: ic revision; a means version a, b means version b, ...etc. sa: process code w39v040faq 2138977a-a12 149obsa
w39v040fa - 34 - 14. package dimensions 32l plcc notes: l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusi o 3. controlling dimension: inches 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 32l stsop min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 0.50 0.00 0 0.22 0.27 ----- 0.21 12.40 8.00 14.00 0.50 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.009 0.010 0.004 ----- 0.008 0.488 0.315 0.551 0.020 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm a a a 2 1 l l 1 y e h d d c b e
w39v040fa publication release date: december 19, 2002 - 35 - revision a2 package dimensions, continued 40l tsop (10 mm x 20 mm) r r 0.08 0.008 0.003 0.02
w39v040fa - 36 - 15. version history version date page description a1 june 19, 2002 - initial issued a2 dec. 19, 2002 23 delete ac test load and waveform. add a note below read/write cycle timing parameter 15 modify pgm mode power supply current (icc) parameter from 20 ma (typ.) to 10 ma (typ.) and 30 ma (max.) to 20 ma (max.) 1, 16, 33 modify fwh mode power supply current (icc) parameter from 40 ma (typ.) to 12.5 ma (typ.) and 60 ma (max.) to 20 ma (max.) 16 modify standby current (isb1) parameter from 20 a (typ.) to 5 a (typ.) and 100 a (max.) to 25 a (max.) headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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